1. Technical Field
The present invention relates to semiconductor devices and methods for manufacturing semiconductor devices, in particular, which are preferably applied to a body-source connection type (source-tied type) transistor formed on a SOI (Silicon on Insulator) wafer.
2. Related Art
MOS transistors formed on a SOI wafer have characteristics such as easiness in element isolation, latch-up-free property, and small source/drain junction capacitance, and thus their utility is attracting attention.
In particular, because fully-depleted SOI transistors can achieve low power consumption and high-speed operations, and they can be easily operated at low voltages, research into operation of SOI transistors in a fully-depleted mode is actively conducted.
However, in order to operate a SOI transistor in a fully-depleted mode, the thickness of the SOI film needs to be thinned down. For this reason, a punch-through phenomenon would likely occur due to the drain induced potential barrier lowering (DIBL: Drain Induced Barrier Lowering), and the drain breakdown voltage of the SOI transistor decreases.
On the other hand, if the SOI film is thickened to prevent the drain breakdown voltage from decreasing, the SOI transistor shifts from a fully-depleted mode to a partially depleted mode, and the low voltage operation of the SOI transistor becomes difficult.
Moreover, Japanese Laid-open Patent Application HEI 5-67785 describes a method for improving the drain breakdown voltage of a SOI transistor and achieving higher operation speeds, in which a concave section is formed in a semiconductor layer of a SOIwafer, and a gate electrode is formed over the concave channel region interposed between source/drain regions.
In addition, in the SOI transistor, when the SOI film thickness is thinned, and the bottoms of the source/drain regions come in contact with the dielectric layer, the body region under the gate electrode is isolated, and the drain breakdown voltage deteriorates by accumulation of impact ionized carriers. Accordingly, there are methods of releasing the impact ionized carriers accumulated in the body region, for example, by connecting the body region under the gate electrode with the source region (body-source connection type), or connecting the body region with the gate electrode (dynamic threshold type).
FIG. 5(a) is a plan view schematically showing a structure of a conventional semiconductor device, FIG. 5(b) is a cross-sectional view taken along lines A2-A2 of FIG. 5(a), and FIG. 5(c) is a cross-sectional view taken along lines B2-B2 of FIG. 5(a).
In FIGS. 5(a)-5(c), a single-crystalline silicon layer 23 is formed on a dielectric layer 21, and the single-crystalline silicon layer 23 is isolated by an element isolation dielectric layer 22. Further, a gate electrode 25 is formed on the single-crystalline silicon layer 23 through a gate dielectric layer 24. Also, a source layer 26a and a drain layer 26b are formed in the single-crystalline silicon layer 23 disposed on both sides of the gate electrode 25. As shown in FIG. 5(b), bottom surfaces of the source layer 26a and the drain layer 26b contact the dielectric layer 21, and a body region below the gate electrode 25 is isolated between the source layer 26a and the drain layer 26b. 
Also, body-source connection layers 27a and 27b that contact the body region below the gate electrode 25 and disposed in a manner to interpose the source layer 26a are formed in the single-crystalline silicon layer 23 on the side of the source layer 26a. Also, an interlayer dielectric film 29 is formed on the single-crystalline silicon layer 23 where the gate electrode 25 is formed, and source contacts C11 and C12 for making contact with the source layer 26a and the body-source connection layers 27a and 27b are formed on the side of the source layer 26a. 
In other words, contact holes K11 and K12 are formed in a manner to cross the borders between the source layer 26a and the body-source connection layers 27a and 27b in the interlayer dielectric film 29, as shown in FIG. 5(c). Further, the source layer 26a and the body-source connection layers 27a and 27b are connected to source wirings 30a and 30b through the contact holes K11 and D12, respectively.
Also, a gate contact C15 for making contact with the gate electrode 25 is formed on the gate electrode 25, and drain contacts C13 and C14 for making contact with the drain layer 26b are formed on the drain layer 26b. 
Here, if an n-channel transistor is assumed to be formed in the single-crystalline silicon layer 23, the single-crystalline silicon layer 23 and the body-source connection layers 27a and 27b are set to be p-type, and the source layer 26a and the drain layer 26b are set to be n+ type.
For this reason, even when holes generated at an edge of the drain flow in the body region, they can be discharged to the source wirings 30a and 30b through the body-source connection layers 27a and 27b, and impact ionized carriers are controlled so as not to accumulate in the body region.
However, the body-source connection type shown in FIGS. 5(a)-5(c) has a problem in that, because the body-source connection layers 27a and 27b are disposed in a manner to contact the source layer 26a, holes, when flowing from the body region to the source layer 26a, cause an impact ionization at a pn junction formed between the body-source connection layers 27a and 27b, and this lowers the drain breakdown voltage.
Therefore, it is an object of the present invention to provide semiconductor devices and methods for manufacturing semiconductor devices, which are capable of suppressing an impact ionization at a border of a body-source connection layer.